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data sheet 04.95 ics for communications primary rate access clock generator and transceiver pract peb 22320 version 2.1
data classification maximum ratings maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. characteristics the listed characteristics are ensured over the operating range of the integrated circuit. typical characteristics specify mean values expected over the production spread. if not otherwise specified, typical characteristics apply at t a =25 c and the given supply voltage. operating range in the operating range the functions given in the circuit description are fulfilled. for detailed technical information about processing guidelines and quality assurance for ics, see our product overview ics for communications peb 22320 revision history current version: 04.95 previous version: 05.93 page subjects (changes since last revision) 10 architecture of the pract 14 input jitter specification 16 jitter attenuator block diagram 17 clock- and synchronization table 18 jitter attenuation characteristics 23 master/slave selection 24 reset 28 delay times 29 dc characteristics 31 recommended oscillator circuits 32, 33 crystal tuning range
peb 22320 general information table of contents page semiconductor group 3 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.1 pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 1.3 system integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.1 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 2.1.1 basic functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 2.1.2 clock and data recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.1.3 input jitter tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 2.1.4 jitter attenuator and clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 2.2.1 basic functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 2.2.2 output jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 2.3 local loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 2.4 remote loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 2.5 bypass jitter attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 2.6 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 2.7 receiver loss of signal indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 2.8 master/slave selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 3 operational description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 3.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 3.1.1 reset with cs pin fixed to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 3.1.2 reset using cs pin to latch programming (a controller is used) . . . . . . . . .26 3.2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 4 electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 4.2 delay times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 4.2.1 delay from xdip/xdin to xl1/xl2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 4.2.2 delay from rl1/rl2 to rdop/rdon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 4.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 4.4 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 4.5 recommended oscillator circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 4.6 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 4.6.1 dual rail interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 4.6.2 system clock interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 4.6.3 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 4.6.4 xtal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
peb 22320 semiconductor group 4 4.7 pulse templates - transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 4.8 overvoltage tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 iom ? , iom ? -1, iom ? -2, sicofi ? , sicofi ? -2, sicofi ? -4, sicofi ? -4c, slicofi ? , arcofi ? , arcofi ? -ba, arcofi ? -sp, epic ? -1, epic ? -s, elic ? , ipat ? -2, itac ? , isac ? -s, isac ? -s te, isac ? -p, isac ? -p te, idec ? , sicat ? , octat ? -p, quat ? -s are registered trademarks of siemens ag. musac ? -a, falc ? 54, iwe ? , sare ? , utpt ? , asm ? , asp ? are trademarks of siemens ag. purchase of siemens i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c-system provided the system conforms to the i 2 c specifications defined by philips. copyright philips 1983.
p-lcc-44 semiconductor group 5 04.95 primary rate access clock generator and transceiver pract peb 22320 preliminary data cmos 1 features ? isdn line interface for 1544 and 2048 kbit/s (t1 and cept) ? data and clock recovery ? transparent to ternary codes ? low transmitter output impedance for a high return loss with reasonable protection resistors (ccitt g.703 requirements for the line input return loss fulfilled) ? adaptively controlled receiver threshold ? programmable pulse shape for t1 applications ? jitter specifications of ccitt i.431 and bellcore tr-nwt-000499 publications met ? wander and jitter attenuation ? jitter tolerance of receiver: 0.5 ui s ? implements local and remote loops for diagnostic purposes ? monolithic line driver for a minimum of external components ? low power, reliable cmos technology ? loss of signal indication for receiver ? clock generator for system clocks the primary rate access clock generator and transceiver pract (peb 22320) is a monolithic cmos device which implements the analog receive and transmit line interface functions to primary rate pcm carriers. it may be programmed or hard wired to operate in 1.544-mbit/s (t1) or 2.048-mbit/s (cept) carrier systems. the pract recovers clock and data using an adaptively controlled receiver threshold. it will meet the requirement of ccitt i.431 and bellcore tr-nwt-000499 issue 5, december 1993 (transport system generic requirements) in case of pulse shape, jitter tolerance and jitter transfer characteristic. type ordering code package peb 22320 n Q67100-A6059 p-lcc-44 (smd)
peb 22320 features semiconductor group 6 specially designed line interface circuits simplify the tedious task of protecting the device against overvoltage damage while still meeting the return loss requirements. the pract is suitable for use in a wide range of voice and data applications such as for connections of digital switches and pbx?s to host computers, for implementations of primary isdn subscriber loops as well as for terminal applications. the maximum range is determined by the maximum allowable attenuation. in the t1 case the pract?s power consumption is mainly determined by the line length and type of the cable.
peb 22320 features semiconductor group 7 1.1 pin configuration (top view) itp04874 6 5 4 3 2 1 44 43 42 41 40 28 27 26 25 24 23 22 21 20 19 18 29 30 31 32 33 34 35 36 37 38 39 7 8 9 10 11 12 13 14 15 16 17 fsc ls0 xtal4 ls1 xtal2 xtal1 ls2 clk16m clk12m sync xl1 n.c. xl2 n.c. rl mode xtin xtip xdin xdip xclk cs rdon rclk clk2m clk2m jatt rl2 ll clk4m clk4m fsc pract peb 22320 ssd v rl1 v ddd rdop xtal3 v dd2 ddr v ssr v v ssx ssx v ddx v ddx v
peb 22320 features semiconductor group 8 1.2 pin definitions and functions pin definitions and functions pin no. symbol input (i) output (o) function 1 v dd2 o reference voltage for tapping the input transformer 2 rl2 i line receiver pin 2 3 ll i local loopback: a high level selects the device for the local loopback mode. 4 5 clk4m clk4m o o system clock 4.096 mhz inverted and non-inverted 6 7 fsc fsc o o 8-khz frame synchronization pulse inverted and non-inverted 8 ls0 i line length select 9 10 xtal4 xtal3 o i crystal connection 12.352 mhz if an external clock generator is used and t1 mode is selected the pract works as a master. 11 ls1 i line length select 12 13 xtal2 xtal1 o i crystal connection 16.384 mhz when an external clock is used, normally if the mode pin is set high, the pract functions as a master. 14 ls2 i line length select 15 clk16m o system clock 16.384 mhz 16 clk12m o system clock 12.352 mhz 17 sync i if a clock is detected at the sync pin the pract synchronizes to this clock (2.048 mhz for cept, 1.544 mhz for t1). (please refer to table 3 ). 18, 19 v ddx i positive power supply for transmit subcircuits 20 xl1 o line transmit pin 1 21, 25 n.c. not connected 22, 23 v ssx i ground for transmit subcircuits 24 xl2 o line transmit pin 2
peb 22320 features semiconductor group 9 26 rl i remote loopback: high level puts the device to the remote loopback mode. 27 mode i master/slave selection if the mode pin is set to a low level the pract functions as a slave. (please refer to table 3 ) 28 29 xtin xtip i i positive and negative test data inputs, active low, full bauded 30 31 xdin xdip i i positive and negative data inputs, active low, full bauded 32 xclk i/o if the t1 mode is selected the xclk is a clock output with a clock frequency of 1.544 mhz. otherwise the xclk is a clock input whose frequency is 2.048 mhz. (please refer to table 3 ) 33 cs ichip select : a low level selects the peb 22320 for a register write operation. 34 v ddd i positive power supply for the digital subcircuits. 35 v ssd i power ground supply for digital subcircuits. 36 37 rdop rdon o o receive data output positive and negative, fully bauded, active low. 38 rclk o receive clock refer to table 3 . 39 40 clk2m clk2m o o system clock 2.048 mhz inverted and non-inverted. 41 v ssr i power ground supply for receive subcircuits. 42 v ddr i positive power supply for the receive subcircuits. 43 jatt i if the jatt pin is set to a low level the jitter attenuator is bypassed. 44 rl1 i line receiver pin 1. pin definitions and functions (cont?d) pin no. symbol input (i) output (o) function
peb 22320 features semiconductor group 10 1.3 system integration figure 1 shows the architecture of a primary access board for data transmission. it exhibits the following functions: ? line interface (peb 22320, pract) ? clock and data recovery (peb 22320, pract) ? jitter attenuation (peb 22320, pract) ? clock generation (peb 22320, pract) ? coding/decoding (peb 2035, acfa) ? framing (peb 2035, acfa) ? elastic buffer (peb 2035, acfa) ? multichannel protocol controller (peb 20320, munich32) ? system adaptation (peb 20320, munich32) ? m p interface (all devices) figure 1 architecture of the pract its04875 tclk/rclk tsp/rsp munich32 peb 20320 peb 2035 acfa sclk sypq pract peb 22320 clk4m fsc fsc clk2m 4.096 mhz 8 khz khz 8 mhz 2.048 memory mpu pc interface
peb 22320 functional description semiconductor group 11 2 functional description figure 2 functional block diagram of the pract jitter attenuator & clock generator loss of signal detection los p recovery data clock & n rrclk remote loop timing & pulseshaper rom d/a local loop receiver driver rl xdin xdip itb04876 rdon rdop rclk xclk (t1) mode sync jatt xtal1, 2, 3, 4 ll rl1 rl2 xl2 xl1 ls0, 1, 2 system clocks xclk (cept) transmit output input receive xtip transmit xtin test data
peb 22320 functional description semiconductor group 12 2.1 receiver 2.1.1 basic functionality the receiver recovers data from the ternary coded signal at the ternary interface and outputs it as 2 unipolar signals at the dual rail interface. one of the lines carries the positive pulses, the other the negative pulses of the ternary signal. the signal at the ternary interface is received at both ends of a center-tapped transformer as shown in figure 3 . . figure 3 receiver configuration the transformer is center-tapped at the pract side. the recommended transmission factors for the different line characteristic impedances are listed in table 1 . table 1 recommended receiver configuration values wired in this way the receiver has a return loss a r > 12 db for 0.025 f b f 0.05 f b , a r > 18 db for 0.05 f b f 1.0 f b and a r > 14 db for 1.0 f b f 1.5 f b , with f b being 2048 khz. thus it complies with ccitt g.703. application t1 cept characteristic impedances [w ] 100 140 (icot) 120 75 r 2 ( 2.5%) [w ] 28.7 39.2 60 60 t 2 : t 1 = t 2 : ( t 11 + t 12 ) 69:52 69:(26 + 26) 69:52 69:(26 + 26) 52:52 52:(26 + 26) 41:52 41:(26 + 26) its00560 t 11 t 12 t 2 r 2 r 2 r l r l v dd line 2 1 2
peb 22320 functional description semiconductor group 13 the receiver is transparent to the logical 1?s polarity and outputs positive logical 1?s on rdop and negative logical 1?s on rdon. rdon and rdop are active low and fully bauded. the comparator threshold to detect logical 1?s and logical 0?s is automatically adjusted to be 45% of the peak signal level. provided the noise is below 10 m v/ ? hz the bit error rate will be less than 10 ?7 . 2.1.2 clock and data recovery an analog pll extracts the internal recovered route clock rrclk from the data stream received at the rl1 and rl2 lines. the pll uses as a reference the system clock clk16m for cept and clk12m for t1 applications. the clock and data recovery is tolerant to long strings of consecutive zeros, because the data sampler will continuously sample data based on its last input. a block diagram of the clock and data recovery circuit is shown in figure 4 . figure 4 clock and data recovery circuit its04877 pd vco filter data sampling p n data rrclk clk16m (cept) clk12m (t1) input data derived from rl 1, 2
peb 22320 functional description semiconductor group 14 2.1.3 input jitter tolerance the pract receiver?s tolerance to input jitter complies to ccitt and bellcore requirements for cept and t1 application. figure 5 shows the curves of the different input jitter specifications stated above as well as the pract performance for the various line codes used at the s1/s2 interfaces. in figure 5 the curves show that the pract at low frequencies has more than 20 db/ decade fall off, and at high frequencies is in a steady state of 0.5 ui (horizontal). figure 5 comparison of input jitter specification and pract performance itd06576 1 10 100 1000 10000 100000 hz 0.1 jitter input tolerance jitter frequency 1 10 100 ui tr-nwt 000499 cat i ii cat 000499 tr-nwt pract cept pract t1 ccitt g.823
peb 22320 functional description semiconductor group 15 2.1.4 jitter attenuator and clock generator the jitter attenuator reduces wander and jitter in the recovered clock which are produced by the line-, clock- and data-recovery characteristics. the attenuator consists of one pll with a tunable crystal oscillator and a 288-bit fifo. to provide for t1 mode a 1.544-mhz clock (xclk) and a 2.048-mhz clock (clk2m) for the system, a second pll is placed in series with the first one (refer to figure 6 ). if the jatt pin is set to low the fifo is bypassed and the propagation delay from rl1, 2 to rdop/rdon is reduced by the pass time of the fifo. after loss of signal detection, the internal pll is synchronized to the 2.048 mhz (cept) provided at the sync pin (1.544 mhz in the case of t1). if this sync pin is not connected or connected to logical zero, the pract switches automatically to master operating mode (refer to table 3 ). with the mode pin a master selection is provided. that means if the mode pin is set to high the master function is selected in which the vco?s of the jitter attenuator are centered ( 50 ppm of the crystal frequencies). if a clock is detected at the sync pin the pract automatically synchronized to this clock. table 2 jitter input tolerance frequency tr-nwt 000499 tr-nwt 000499 pract pract hz ccitt g.823 cat i cat ii cept t1 12.9 10 5 10 20 1.5 192.9 10 500 5 90 70 2400 1.5 5.8 4.5 6430 0.3 8000 0.1 1.15 0.95 10000 0.95 0.8 18000 0.2 0.62 0.58 20000 0.58 0.55 25000 0.55 0.55 40000 0.1 0.3 0.5 0.5 50000 0.55 0.55 100000 0.55 0.55
peb 22320 functional description semiconductor group 16 the jitter attenuator meets the jitter transfer requirements of the bellcore tr-nwt 000 499 and rec. i.431 (refer to figure 7 and table 4 ). the amount of generated output jitter when no input jitter is shown in table 5 . figure 6 jitter attenuator block diagram itb04879 pd vco 256 2 4 16.384 mhz khz 8 2 mhz 4 mhz mhz 16 12 mhz mhz 12.352 8 193 vco pd mode 193 8 khz 256 1.5 mhz (xclk-t1) t1 sync los rclk rdon rdop recovery clock & data rl1, 2 n data data p rrclk fifo r w jatt _ < _ < _ < _ < _ < _ < _ <
peb 22320 functional description semiconductor group 17 table 3 clock and synchronization table jatt = 1: jitter attenuator enabled 12 m = 12.352 mhz rrclk = internal recovered route clock mode = 0 slave mode selected jatt = 0: bypass jitter attenuator 16 m = 16.384 mhz sync = 0: input tied to low mode = 1: master mode selected 4 m = 4.096 mhz sync = 2 m: input connected to 2 m 8 k = 8.0 khz los = 0: input above receiver threshold 2 m = 2.048 mhz sync = 1.5 m: input connected to 1.5 m = don ?t care los = 1: input below receiver threshold 1.5 m = 1.544 mhz = no connection pin jatt int. sig los pin sync pin mode pin ls0..2 pin xtal3 pin xtal4 pin xtal1 pin xtal2 system clocks 4m, 2m, 8k derived from pin xclk pin rclk 10 x 0 t1 12 m crystal 16 m crystal 16 m crystal sync. on xclk output: 1.5 m sync. on rrclk =1.5 m 1 1 0 0 t1 12 m crystal 16 m crystal 16 m crystal sync. on xclk output: 1.5 m, freq. centered =1.5 m 1 1 1.5 m 0 t1 12 m crystal 16 m crystal 16 m crystal sync. on xclk output: 1.5 m sync. on sync =1.5 m 1 x 1.5 m 1 t1 12 m crystal 16 m crystal 16 m crystal sync. on xclk output: 1.5 m sync. on sync =1.5 m 1 x 0 1 t1 12 m crystal 16 m crystal 16 m crystal sync. on xclk output: 1.5 m freq. centered =1.5 m 1 x x x t1 12 m in n.c. 16 m crystal 16 m crystal sync. on xclk output: 1.5 m sync. on xtal3 =1.5 m 10 x 0 cept x x 16 m crystal 16 m crystal sync. on rrclk input (2 m from acfa) =2 m 1 1 0 0 cept x x 16 m crystal 16 m crystal sync. freq. centered input (2 m from acfa) =2 m 1 1 2 m 0 cept x x 16 m crystal 16 m crystal sync. on sync input (2 m from acfa) =2 m 1 x 2 m 1 cept x x 16 m crystal 16 m crystal sync. on sync input (2 m from acfa) =2 m 1 x 0 1 cept x x 16 m crystal 16 m crystal sync. freq. centered input (2 m from acfa) =2 m 1 x x x cept x x 16 m in n.c. 16 m in input (2 m from acfa) =2 m 00 x 0 t1 12 m crystal 16 m crystal 16 m crystal sync. on xclk output: 1.5 m sync. on rrclk =rrclk 0 1 0 0 t1 12 m crystal 16 m crystal 16 m crystal sync. on xclk output: 1.5 m, freq. centered =rrclk 0 1 1.5 m 0 t1 12 m crystal 16 m crystal 16 m crystal sync. on xclk output: 1.5 m sync. on sync =rrclk 0 x 1.5 m 1 t1 12 m crystal 16 m crystal 16 m crystal sync. on xclk output: 1.5 m sync. on sync =rrclk 0 x 0 1 t1 12 m crystal 16 m crystal 16 m crystal sync. on xclk output: 1.5 m freq. centered =rrclk 0 x x x t1 12 m in n.c 16 m crystal 16 m crystal sync. on xclk output: 1.5 m sync. on xtal3 =rrclk 00 x 0 cept x x 16 m crystal 16 m crystal sync. on rrclk input (2 m from acfa) =rrclk 0 1 0 0 cept x x 16 m crystal 16 m crystal sync. freq. centered input (2 m from acfa) =rrclk 0 1 2 m 0 cept x x 16 m crystal 16 m crystal sync. on sync input (2 m from acfa) =rrclk 0 x 2 m 1 cept x x 16 m crystal 16 m crystal sync. on sync input (2 m from acfa) =rrclk 0 x 0 1 cept x x 16 m crystal 16 m crystal sync. freq. centered input (2 m from acfa) =rrclk 0 x x x cept x x 16 m in n.c. 16 m in input (2 m from acfa) =rrclk x n.c.
peb 22320 functional description semiconductor group 18 figure 7 jitter attenuation characteristics table 4 jitter transfer characteristics frequency ccitt g. 735 tr-nwt 000499 pract pract hz ccitt i.431 cat i to cat ii cept t1 0.3 0.00 1 30.00 ? 20.00 10 0.5 0.10 30 ? 20.00 ? 40.00 40 0.5 100 itd06577 0.1 hz -60 jitter transfer characteristics jitter frequency ccitt g.735 ccitt i.431 pract cept pract t1 1 10 100 1000 10000 100000 i cat 000499 tr-nwt cat i to -50 -40 -30 -20 -10 0 2 db
peb 22320 functional description semiconductor group 19 table 5 generated output jitter 200 250 300 ? 39.40 ? 60.00 350 400 ? 19.50 9650 1000 1412 2500 ? 34.07 3000 ? 60.00 ? -80.00 10000 15000 ? 19.50 ? 49.63 specification measurement filter bandwidth output jitter lower cutoff upper cutoff (ui peak to peak) i.431 20 hz 700 hz 100 khz 100 khz 0.125 0.02 pub 62411 dez. 90 10 hz 8 khz 10 hz 8 khz 40 khz 40 khz 0.02 0.025 0.025 broad band 0.05 ets 300 011 40 hz 100 khz 0.11 table 4 jitter transfer characteristics (cont?d) frequency ccitt g. 735 tr-nwt 000499 pract pract hz ccitt i.431 cat i to cat ii cept t1
peb 22320 functional description semiconductor group 20 2.2 transmitter 2.2.1 basic functionality the transmitter transforms unipolar data to ternary (alternate bipolar) return to zero signals of the appropriate shape. the unipolar data is provided at xdip (positive pulses) and xdin (negative pulses), synchronously with the transmit clock xclk. xdip and xdin are active low and full bauded. data is sampled on the falling edge of the input clock (xclk). the input clock (xclk) must be derived from the (system) clocks generated by the pract. this ensures the recommended fixed relationship between xlck and internal generated clock (4 times xclk) for the pulse shaper. the transmitter includes a programmable pulse shaper to satisfy the requirements of the at&t technical advisory # 34 at the cross connect point for t1 applications. the pulse shaper is programmed via the line length selection pins ls0, ls1 and ls2. for t1 application the line length selection supports both low capacitance cable with a characteristic line capacitance of c? 40 nf/km = 65 nf/mile (e.g. mat, icot) and higher capacitance cable with a characteristic line capacitance of 40 nf/ km c? 54 nf/km (65 nf/mile c? 87 nf/mile) e.g. abam, pic and pulp cables. this ensures that for various cable types the signal at the dsx-1 cross connect point complies with the pulse shape of the at&t technical advisory # 34. the line length is selected programming the ls0, ls1 and ls2 pins as shown for typical values in table 6 . table 6 line length selection note: * for icot-cable the characteristic impedance is 140 w by selecting an all-zero code for ls0, ls1 and ls2 the pract can be adapted for cept applications. ls2 ls1 ls0 pic/pulp cable 24 awg range/m icot cable range/m* 000cept ? ? 001t1/g.7030?500?80 0 1 0 t1 20 ? 80 65 ? 145 0 1 1 t1 60 ? 130 130 ? 210 1 0 0 t1 110 ? 200 195 ? 275 1 0 1 t1 140 ? 230 260 ? 340 1 1 0 t1 210 ? 290 325 ? 405 1 1 1 t1 270 ? 320 390 ? 470
peb 22320 functional description semiconductor group 21 the pulse shape according to ccit g.703 (1544-kbit/s interface) is achieved by using the same line length selection code as for the lowest t1 cable range. to switch the device into a low power dissipation mode, xdip and xdin should be held high. the transmitter requires an external step up transformer to drive the line. the transmission factor and the source serial resistor values can be seen in figure 8 and table 7 for the various applications. figure 8 transmitter configuration table 7 transmitter configuration values wired in this way the transmitter has a return loss a r > 8 db for 0.025 f b f 0.05 f b , a r > 14 db for 0.05 f b f 1.0 f b and a r > 10 db for 1.0 f b f 1.5 f b , with f b being 2048 khz (cept applications). a termination resistor of 120 w is assumed. in t1 applications the return loss is higher than 10 db. please note, that the transformer ratio at the receiver is half of that at the transmitter. the same type of transformer can thus be used at the receiver and at the transmitter. at the transmitter the two windings are connected in parallel, at the receiver in series. thus, unbalances are avoided. application t1 cept characteristic line impedance [ w] 100 140 (icot) 120 75 t 11 : t 2 = t 12 : t 2 26:69 26:69 26:52 26:41 r 1 ( 2.5%) [ w] 4.3 6 15 15 its00562 t 11 t 12 t 2 r 1 r 1 line xl1 2 xl
peb 22320 functional description semiconductor group 22 2.2.2 output jitter in the absence of any input jitter the pract generates the output jitter, which is specified in table 5 . note: the generated output jitter on the line is the same as the output jitter of the system clocks. 2.3 local loopback the local loopback mode disconnects the receive lines rl1 and rl2 from the receiver. instead of the signals coming from the line the data provided at xtip and xtin are routed through the receiver. the xdin and xdip signals continue to be transmitted on the line. the local loopback occurs in response to ll going high. 2.4 remote loopback in the remote loopback mode the clock and data recovered from the line inputs rl1 and rl2 are routed back to the line outputs xl1 and xl2 via the transmitter. as in normal mode they are also output at rdop and rdon. xdip and xdin are disconnected from the transmitter. the remote loopback mode is selected by a high rl signal. 2.5 bypass jitter attenuator if the jatt pin is set to low the jitter attenuator (fifo) is bypassed and the propagation delay from the line to the dual rail interface is reduced by the path time of the fifo. also in this mode the jitter in the system clocks (clk2m, clk4m, fsc) is attenuated. 2.6 microprocessor interface the pract is fully controlled by six parallel data lines (ls0, ls1, ls2, ll, rl and jatt) and one control line (cs ). to adapt the device to a standard microprocessor interface the low state of cs is decoded from the microprocessor address, cs , wr and ale lines. to hardwire the chip, cs must be fixed to ground. 2.7 receiver loss of signal indication in the case that the signal at the line receiver input (pins rl1, rl2) becomes smaller than v in 0.3 v op loss of signal is indicated. this voltage value corresponds to a line attenuation of about 14 db in the cept case. this is performed by turning both signals rdop, rdon after at least 32 bits simultaneously to 5 v, i.e. a logical 0 on both lines. the following acfa processes this indication for the system. in this mode the pract synchronizes to the clock at the sync pin.
peb 22320 functional description semiconductor group 23 2.8 master/slave selection if the mode pin is set to high and the sync pin is not connected or connected to v ss the pract works as a master for the system. the vco?s of the jitter attenuator are centered ( 50 ppm of the crystal frequencies) and the system clocks are stable (divided from the vco frequencies). if a clock (2.048 mhz for cept, 1.544 mhz for t1) is detected at the sync pin the pract synchronizes automatically to this clock. in master mode, the pract is independent from the receiver loss of signal detection. note: the mode pin can not be controlled by the m p interface and requires cmos levels as input signals. it must always be connected either to v dd or v ss . a voltage of 2.5 v at the mode pin switch the pract into test mode.
peb 22320 operational description semiconductor group 24 3 operational description 3.1 reset after power up resetting the device is necessary to synchronize the internal circuitries. after reset a stabel rclk is available after 65536 clock cycles. this results in 32 ms in cept mode and 42.5 ms in t1 mode. a reset can be performed by two ways. 3.1.1 reset with cs pin fixed to v ss in this reset operation the cs pin is normally hardwired to v ss . before giving a reset the operational mode has to be selected (cept, t1) by setting the pins ls2, ls1, ls0 to 000 for cept-application, to 001 for ntt-application or 001 ? 111 for t1 application. a reset is made by simultaneously setting both rl and ll to high (cs = 0) for at least 1 m s. reset will be initiated on the falling edge of rl or ll, the one that falls first. the following figures explain the procedure in some examples. figure 9 resetting pract for cept applications t 1. 2. itd04881 1. start of reset 2. end of reset ll rl ls0 ls1 ls2 cs s m 1
peb 22320 operational description semiconductor group 25 figure 10 resetting pract for cept applications and setting local loop with jitter attenuation figure 11 resetting pract for t1 applications (max. line length selected) and setting remote loop note: if the pract is initiated for t1 applications the line length selection can be changed without a new reset. t 1. 2. itd04882 1. start of reset 2. end of reset and local loop is initiated jatt rl ls0 ls1 ls2 cs ll t 1. 2. itd04883 1. start of reset 2. end of reset, regular operation in t1 mode ll rl ls0 ls1 ls2 cs 3. 3. remote loop is initiated
peb 22320 operational description semiconductor group 26 3.1.2 reset using cs pin to latch programming (a controller is used) reset is done by setting the pins rl and ll to logical 1 for at least 1 m s and latching these values into pract by a rising edge at pin cs . the selection of cept, t1 applications is achieved by setting the pins ls2, ls1, ls0 simultaneously with the reset to 000 for cept application or a t1 line length code (001 ? 111 see table 6 ). the logical level of the rl, ll, ls2, ls1, ls0, jatt input parts are latched with the rising edge of the cs . refer to figure 20 . the following figures explain the procedure in some examples. figure 12 resetting pract for cept applications and jitter attenuation figure 13 resetting pract for cept application and setting remote loop t 1. itd04884 1. start of reset 2. end of reset, regular operation in cept mode ll rl cs 2. ls0, 1, 2 s m 1 jatt t 1. itd04885 1. start of reset 2. end of reset and setting remote loop ll rl cs 2. ls0, 1, 2
peb 22320 operational description semiconductor group 27 figure 14 resetting pract for t1 applications and changing line length code figure 15 resetting pract for t1 application and setting local loop 3.2 operation the pract is in normal operation as soon as the reset phase is finished. the cs pin is activated again only when pract is reprogrammed (for example setting a loop or changing line length code). that means cs pin could be kept high for normal operation. t 1. itd04886 1. start of reset 2. end of reset and setting line length code, regular operation in t1 mode ll rl cs 2. 3. changing line length code, regular operation in t1 mode with ls0, 1, 2 001 xxx xxx 001 xxx 3. 010 xxx xxx changed line length code t 1. itd04887 1. start of reset 2. end of reset and setting local loop and ll rl cs 2. line length code ls0, 1, 2 111 xxx xxx 111 xxx
peb 22320 electrical specification semiconductor group 28 4 electrical specification 4.1 absolute maximum ratings 4.2 delay times 4.2.1 delay from xdip/xdin to xl1/xl2 the delay from xdip/xdin to xl1,xl2 is 770 ns in t1 mode and 860 ns in cept mode. this relates to the falling edge of the xclk and the leading edge of xl1 or xl2. 4.2.2 delay from rl1/rl2 to rdop/rdon the delay from rl1/rl2 to rdop/rdon is given with 700 ns in t1 mode and 540 ns in cept mode. this relates to the leading edge of the rl1 or rl2 to the falling edge of rdop or rdon. parameter symbol limit values unit voltage on any pin with respect to ground v s ? 0.4 to v dd + 0.4 v ambient temperature under bias t a 0 to 70 c storage temperature t stg ? 65 to 125 c
peb 22320 electrical specification semiconductor group 29 4.3 dc characteristics t a = 0 to 70 c; v dd = 5 v 5%, v ss = 0 v dc characteristics parameter symbol limit values unit test condition pins min. max. l-input voltage v il ? 0.4 0.8 v all pins except mode, rlx, xlx xtalx, v dd2 , sync h-input voltage v ih 2.0 v dd + 0.4 v l-output voltage v ol 0.45 v i ol = 2 ma h-output voltage v oh 2.4 v i oh = ? 400 m a h-output voltage v oh v dd ? 0.5 v i oh = ? 100 m a input leakage current i li 1 m a0v < v in < v dd to 0v output leakage current i lo 0v < v out < v dd to 0v peak voltage of a mark (cept) v xcept 2.7 3.3 v wired according figure 8 and table 7 xl1, xl2 peak voltage of a mark (t1) v xt1 1.8 3.4 v t1 application: depending on line length transmitter output impedance r x 0.3 w transmitter output current i x 50 ma cept application 150 ma t1 application: depending on line length receiver input peak voltage of a mark v r 1) 0.4 2.5 v rl1, rl2 loss of signal threshold v los 0.3 v receiver input threshold v rth 45 % voltage at v dd2 v dd2 2.4 2.6 v
peb 22320 electrical specification semiconductor group 30 4.4 characteristics t a = 25 c; v dd = 5 v 5 %, v ss = 0 v 1) measured against v dd2 l-input voltage v xtalil ? 0.4 1.0 v xtal1, xtal2, xtal3, xtal4 h-input voltage v xtalih 4.0 v dd + 0.4 v input leakage current i xtali 1 m a0v v in v dd to 0v operational power supply current i cc 40 110 ma cept application 55 190 ma t1 application, min value for all zeros, max value for all ones and max. line length for t1 appl. l-input voltage v il ? 0.4 0.8 v mode, sync h-input voltage v ih 4.0 v dd + 0.4 v input leakage current i li1 i li2 i li3 i li4 800 100 800 200 m a m a m a m a v il = 0.8 v v il = 0.1 v v ih = 4 v v ih = v dd parameter symbol limit values unit pins min. max. input capacitance c in 10 pf all except rlx, xlx, xtalx output capacitance c out 15 pf all except rlx, xlx, xtalx input capacitance c in 7pfrlx output capacitance c out 20 pf xlx dc characteristics (cont?d) parameter symbol limit values unit test condition pins min. max.
peb 22320 electrical specification semiconductor group 31 4.5 recommended oscillator circuits figure 16 oscillator circuits in cept mode if an external source is connected to xtal1, the pract works, independent of the mode pin, in master mode. in t1 mode if an external source is connected to xtal3, the pract works, independent of the mode pin, in master mode. this operational mode requires a crystal (16.384 mhz) at pins xtal1 and xtal2. the frequency is locked to the external source. the jitter attenuator requires unique performance specifications for the crystals. the following typical crystal parameters will meet this specifications: ? motional capacitance c 1 = 25 ff min ? shunt capacitance c 0 = 7 pf max ? load capacitance c l = 18 pf typ, f 0 = 16.384 mhz c l = 10 pf typ, f 0 = 12.352 mhz ? resonance resistance r r 25 w its04888 xtal1 (xtal3) (xtal4) xtal2 pract 16.384 (12.352 mhz mhz) 14 pf pf 14 pract xtal2 (xtal4) (xtal3) xtal1 external oscillator signal n.c. crystal oscillator mode (slave mode/ master mode) driving from external source (master mode) (12.352 16.384 mhz) mhz (4 pf) c l =
peb 22320 electrical specification semiconductor group 32 pract tuning range 16.384 mhz pll crystal specified for c l = 18 pf figure 17 16.384-mhz crystal tuning range itd06578 14 -150 -100 -50 0 50 100 150 ppm 16 18 20 22 24 pf 26 d f f 0 c l
peb 22320 electrical specification semiconductor group 33 pract tuning range 12.352 mhz pll crystal specified for c l = 10 pf figure 18 12.352-mhz crystal tuning range itd06579 6 -250 ppm 8 pf d f f 0 c l 12 10 16 14 18 -200 -150 -100 -50 0 50 100 150 200 250
peb 22320 electrical specification semiconductor group 34 4.6 ac characteristics t a = 0 to 70 c; v dd = 5 v 5 % figure 19 input/output waveforms for ac tests except from the line interface, inputs are driven at 2.4 v for a logical 1 and 0.4 v for a logical 0. timing measurements are made at 2.0 v for a logical 1 and at 0.8 v for a logical 0. ac testing input/output waveforms are shown in figure 19 . 4.6.1 dual rail interface rdop, rdon, xdip, xdin, xtip, xtin are active low. figure 20 timing of the dual rail interface its00621 = 150 load c test under device 0.45 2.4 2.0 0.8 0.8 2.0 test points pf itt04889 t cpr cprh tt cprl droh t t dros rclk rdon xdin xclk dris tt drih cpxl t t cpxh cpx t xtin rdop, xtip, xdip,
peb 22320 electrical specification semiconductor group 35 parameter symbol limit values unit pcm 30 pcm 24 min. max. min. max. rclk clock period t cpr typ. 488 typ. 648 ns rclk clock period low t cprl 200 260 ns rclk clock period high t cprh 200 260 ns dual rail output setup t dros 200 260 ns dual rail output hold t droh 200 260 ns xclk clock period t cpx typ. 488 typ. 648 ns xclk clock period low t cpxl 200 250 ns xclk clock period high t cpxh 200 250 ns dual rail input setup t dris 25 25 ns dual rail input hold t drih 25 25 ns
peb 22320 electrical specification semiconductor group 36 4.6.2 system clock interface figure 21 timing of the system clock interface itt04890 t cp16 cp16h t t cp16l t cp4 cp4h t cp4l t t cp2l t cp2h cp2 t ss tt sh cp12l tt cp12h cp12 t t cp15 cp15h t cp15l t clk16m clk4m clk4m clk2m clk2m fsc fsc clk12m xclk (t1)
peb 22320 electrical specification semiconductor group 37 system clock interface timing parameter values parameter symbol limit values unit min. max. clk16m period 16 mhz t cp16 typ. 61 ns clk16m period 16 mhz low t cp16l 20 ns clk16m period 16 mhz high t cp16h 20 ns clk4m period 4 mhz t cp4 typ. 244 ns clk4m period 4 mhz low t cp4l 110 ns clk4m period 4 mhz high t cp4h 110 ns clk2m period 2 mhz t cp2 typ. 488 ns clk2m period 2 mhz low t cp2l 220 ns clk2m period 2 mhz high t cp2h 220 ns fsc setup time t ss 110 ns fsc hold time t sh 240 ns clk12m period 12 mhz t cp12 typ. 81 ns clk12m period 12 mhz low t cp12l 30 ns clk12m period 12 mhz high t cp12h 30 ns xclk period 1.5 mhz t cp15 typ. 648 ns xclk period 1.5 mhz low t cp15 l 300 ns xclk period 1.5 mhz high t cp15 h 300 ns
peb 22320 electrical specification semiconductor group 38 4.6.3 microprocessor interface figure 22 timing of the microprocessor interface parameter symbol limit values unit min. max. cs pulse width t wc 60 ?ns data setup time to cs t dw 35 ? ns data hold time from cs t wd 10 ? ns cycle time t cyc 120 ns itt04891 t cyc wc t wd t t dw cs 2) data ls0, rl, (jatt, ll, 1,
peb 22320 electrical specification semiconductor group 39 4.6.4 xtal timing figure 23 timing of xtal1/xtal3 xtal1/xtal3 timing parameter values note: if an external clock is used the pract works as a master. please refer to pin definitions. parameter symbol limit values unit condition min. typ. max. clock period of crystal/ clock t p 61 81 ns xtal1 xtal3 high phase crystal/clock t wh 20 30 ns xtal1 xtal3 low phase of crystal/clock t wl 20 30 ns xtal1 xtal3 itt04892 xtal1 wl t t wh p t 3.5 v v 0.8 xtal3
peb 22320 electrical specification semiconductor group 40 4.7 pulse templates - transmitter the pract meets both ccitt and t1 pulse template requirements. figure 24 pulse template at the transmitter output for cept applications itd00573 10 % 10 % % 10 10 % % 10 10 % 20 % 269 ns (244 + 25) (244 - 50) ns 194 219 ns (244 - 25) ns 244 (244 + 244) ns 488 % 0 50 % % v =100 nominal pulse % 20 20 %
peb 22320 electrical specification semiconductor group 41 figure 25 t1 pulse shape at the cross connect point table 8 t1 pulse template corner points at the cross connect point maximum curve minimum curve (0 0.05) (0, ? 0.05 (250, 0.05) (350, ? 0.05) (325, 0.80) (350, ? 0.50) (325, 1.15) (400, 0.95) (425, 1.15) (500, 0.95) (500, 1.05) (600, 0.90) (675, 1.05) (650, 0.50) (725, ? 0.07) (650, ? 0.45) (1100, 0.05) (800, ? 0.45) (1250, 0.05) (925, ? 0.20) (1100, ? 0.05) (1250, ? 0.05) itd00574 % 100 = v 50 % 0 -50 % 0 250 500 750 1000 ns t normalized amplitude
peb 22320 electrical specification semiconductor group 42 figure 26 pulse shape according to ccitt g.703 4.8 overvoltage tolerance to prevent the pract from being damaged by overvoltage (i.e. from lightning), external devices like diodes or resistors have to be connected to one or both sides of the line interface transformers. thus, overvoltage peaks are cut off. however, some residual overvoltage may remain. the pract simplifies the task of designing external protection circuits. its transmitter exhibits a low line impedance so that reasonable external resistors can be connected to the line outputs. figure 8 with the element values of table 7 gives an example of how an overvoltage protection against residual overvoltages at the ternary interface can be accomplished. the solution shown also meets the stated return loss requirements. a similar consideration applies to the receiver. the resistors r2 of figure 3 provide protection against residual overvoltages by attenuating voltages of both polarities across rl1 and rl2. the maximum input current allowed to reach the pract pins under overvoltage conditions is given as a function of the width of a rectangular input current pulse according to figure 27 . figure 29 shows the curve of the maximum allowed input current across the pins rl1 and rl2, figure 28 across the pins xl1 and xl2. itd00575 0.3 1.2 50 ns 50 ns 0.7 0.7 3t 8 -- 4 t0t 8 t 4 3t 8 t 2 t = 1/1544 khz 0 1.5 3.0 v
peb 22320 electrical specification semiconductor group 43 figure 27 measurement of overvoltage stress figure 28 tolerated input current at the xl1, xl2 pins its04893 i t i p t wi condition: all other pins grounded falc tm -54 itd00578 1 -9 10 -6 10 -3 10 1 10 db/decade r i 2 w a s i t p wi 10 -2 10 50 100 0.5 5 2x10 -1 _ <
peb 22320 electrical specification semiconductor group 44 figure 29 tolerated input current at the rl1, rl2 pins itd00577 20 10 1 -1 10 -10 -9 10 -6 10 -4 10 -3 10 1 6x10 10 -1 2x10 -1 a s p i wi t w 300 db/decade 10 r < i _
peb 22320 package outlines semiconductor group 45 5 package outlines plastic package, p-lcc-44 (smd) (plastic leaded chip carrier) gpl05102 sorts of packing package outlines for tubes, trays etc. are contained in our data book ?package information?. dimensions in mm smd = surface mounted device

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